Modern modulators for phase or frequency modulation and which are used in transmitters for digital communication systems are frequently based on the principle of direct modulation of a frequency synthesizer, which is in turn in the form of a PLL.
FIG. 1 shows one typical version of a modulator such as this, which is described in the publication “A simplified continuous phase modulator technique” by T. A. Riley et al., IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Vol. 41, No. 4, pages 321-328, May 1994. The essence of the modulator is a PLL which acts as a frequency synthesiser and has a closed control loop which includes a phase frequency detector 1 with a charge pump, a loop filter 2, a voltage controlled oscillator 3 (VCO) and a frequency divider 4 whose division ratio is variable.
During steady-state operation in the PLL, the frequency fout of the signal at the output 5 of the PLL is:fout=N·fref  (1)
In this case, fref describes the frequency of the signal at the reference frequency input 6, and N describes the division ratio of the frequency divider 4.
For modulation of the PLL, the PLL has a modulation input 7 via which the division ratio N of the frequency divider 4 can be varied. A modulator such as this with only one modulation input is also referred to as a one-point modulator. When the division ratio N is varied, the frequency fout of the signal at the output 5 varies in accordance with equation 1. A circuit as illustrated in FIG. 1 can thus be used to produce frequency modulation as well as phase modulation (since the frequency and phase are linked via the integral).
In order to drive the modulation input 7, a digital (in this case: binary) modulation data signal 8 is modulated by means of a digital pulse shaping filter 9. The pulse shaping filter 9 is used to increase the spectral efficiency of the modulation signal, that is to say the output signal from the pulse shaping filter 9 has a narrower bandwidth than the original modulation data signal 8. The digital output signal from the pulse shaping filter 9 has a signal 10 for indication of the channel (also referred to as a channel word) superimposed on it. The resultant digital signal is received by a sigma-delta modulator 11 which drives the modulation input 7 of the PLL. The sigma-delta modulator 11 uses the resultant digital signal to produce a signal which fluctuates over time (also referred to as a “dithering”), so that the division ratio N effectively represents a fractional number rather than a natural number. A modulator as illustrated in FIG. 1 is thus also referred to as a sigma-delta fractional N modulator. The use of a sigma-delta modulator for generation of an effectively fractional division ratio is in principle not essential, but increases the modulation resolution and thus reduces the phase noise.
The circuit illustrated in FIG. 1 has the disadvantage that the bandwidth of the transfer function of the PLL from the modulation input 7 to the output 5 of the PLL (referred to for short as the bandwidth of the PLL in the following text) must satisfy two mutually contradictory conditions. On the one hand, the bandwidth must be designed to be as narrow as possible in order to produce as little noise as possible at the output of the modulator. On the other hand, it is necessary to ensure for the transmission of the modulation data signal 8 that the bandwidth of the PLL is wider than the bandwidth of the signal applied to the modulation input 7, that is to say the bandwidth must be chosen to be appropriately high for transmission of a modulation data signal 8 at as a high a data rate as possible. For this reason, as high a data rate as possible and as little noise as possible on the output side can be combined with one another only with difficulty with the concept as illustrated in FIG. 1.
Owing to component scatters, temperature fluctuations and operating-voltage fluctuations practical implementation of a modulator as illustrated in FIG. 1 is subject to the problem that the PLL bandwidth as provided by the developer is subject to major tolerances during operation. In order to ensure that the modulation data signal 8 is transmitted at a predetermined data rate, the bandwidth of the PLL must accordingly be chosen to be higher, in order to cover these tolerances. In general, the bandwidth which is actually used during operation is thus considerably too high, thus unnecessarily increasing the phase noise in the modulator.
The dissertation “Techniques for High Data Rate Modulation and Low Power Operation of Fractional-N Frequency Synthesizers” by Michael Henderson Perrot, Massachusetts Institute of Technology, September 1997, describes a concept for sigma-delta fractional N modulators in which the bandwidth of the signal which is applied to the modulation input 7 can be chosen to be wider than the bandwidth of the PLL, so that the data rate of the modulation data signal 8 can be increased. In this case, the complexity and power losses in the sigma-delta fractional N modulator are only slightly higher than those which occur in the modulator illustrated in FIG. 1.
FIG. 2 shows the sigma-delta fractional N modulator as proposed by Perrot. Circuit parts and signals which are provided with the same reference symbols in FIG. 1 and FIG. 2 in this case correspond to one another. The increase in the data rate of the modulation data signal 8 is achieved by the use of a digital compensation filter 12, which is connected downstream from the pulse shaping filter 9. The transfer function of the compensation filter 12 in this case corresponds to the inverse of the transfer function of the PLL from the modulation input 7 to the output 5 of the PLL, and the resultant transfer function of the compensation filter 12 and of the PLL is thus at least in theory constant, so that the data rate of the modulation data signal 8 can be chosen to be considerably wider than the bandwidth of the PLL. The compensation filter 12 can in this case be combined with the pulse shaping filter 9 as a single digital FIR filter (FIR=finite impulse response). The filter coefficient for the pulse shaping filter 9, which are stored in a ROM (ROM=read only memory) must be adapted as appropriate for integration of the compensation filter 12 in the pulse shaping filter 9.
One major factor for the modulator concept illustrated in FIG. 2 is that the use of the additional compensation filter 12 does not increase the noise, since the provision of the compensation filter 12 effectively corresponds only to a change in the pulse shaping filter 9, so that the analogue circuit section is not affected.
The modulator concept illustrated in FIG. 2 has the disadvantage that the matching between the digital compensation filter 12 and the analogue PLL, in particular the analogue loop filter 2, is subject to stringent requirements. The bandwidth of the PLL can fluctuate owing to component tolerances in the analogue filter components of the analogue loop filter 2, or owing to scatter in the control gradient of the VCO 3. Thus, in practice, it is impossible to completely compensate a transfer function of the PLL for the transfer function of the digital compensation filter 12, taking into account manufacturing tolerances. Fluctuations in the operating temperature and supply voltage also have a similar negative influence.
FIG. 3 illustrates an alternative concept to that illustrated in FIG. 2 for increasing the data rate of a sigma-delta fractional N modulator. In contrast to the 1-point modulators illustrated in FIG. 1 and FIG. 2, the sigma-delta fractional N modulator illustrated in FIG. 3 is a 2-point modulator. Circuit parts and signals which are provided with the same reference symbols in FIG. 2 and FIG. 3 in this case correspond to one another. In the case of the 2-point modulator which is illustrated in FIG. 3, the modulation data signal 8 is fed to the PLL not only via the control input 7 of the frequency divider 4 (analogously to FIG. 1 and FIG. 2), but also via a second control input 14 of the VCO 3. In this case, the VCO 3 is modulated directly via the second control input 14. Furthermore, a digital/analogue converter and an analogue pulse shaping filter are required to drive the VCO 3 via the second control input 14, and these are formed by the circuit block 13. In the case of the 2-point modulator illustrated in FIG. 3, the low-frequency signal components of the modulation data signal 8 modulate the PLL via the frequency divider 4, while the high-frequency signal components of the modulation data signal 8, predominantly at frequencies higher than the bandwidth of the PLL, modulate the VCO 3 directly.
The 2-point modulator illustrated in FIG. 3 has the disadvantage that the additional circuit block 13 increases the power consumption of the 2-point modulator in comparison to conventional 1-point modulators. Furthermore, the concept illustrated in FIG. 3 has similar disadvantages to those of the concept illustrated in FIG. 2, that is to say the matching between the digital modulation path and the analogue modulation path is subject to stringent requirements for correct operation of the modulator illustrated in FIG. 3.